1. Field of the Invention
This invention relates generally to communication systems using Pseudo-Noise (PN) coding techniques, and pertains more specifically to methods and systems for timing correction for fast PN acquisition.
2. Prior Art
Numerous multiple access communication systems have been developed for transferring information among a large number of system users. Techniques employed by such multiple access communication systems include time division multiple access (TDMA), frequency division multiple access (FDMA), and AM modulation schemes, such as amplitude companded single sideband (ACSSB), the basics of which are well known in the art.
In Spread Spectrum (SS) or TDMA-SS transmission systems, a succession of short-duration bursts emanating from a number of different stations are presented to a demodulator. Each burst may contain data frames from one or more data channels. Each data frame generally contains synchronization or sync word and a data payload area.
Minimizing PN acquisition time for burst signals is necessary for fast PN acquisition and generally requires estimating chip time alignment. However, until a burst is detected, there is no knowledge of the signal timing.
Current implementations also require iterative estimations, as in the case with an early-late gate in a feedback loop. Current implementations also require that the PN timing already be within a PN chip range as in the case with an early-late gate method. This approach does not allow timing errors to be determined and compensated as soon as a parallel correlator detects the burst signal such that the next received PN chip can be correctly sampled at the optimum position and demodulated by the receiver. This “pull-in” time restricts receiving the next PN chip sampled at the optimum timing. Current implementations also require calculations to be performed over a training sequence or over the initial portion of the burst, again requiring extra time as well as using a portion of the burst signal payload for timing purposes rather than data transfer.
Therefore, it is desirable for a system and method for fast PN timing estimate not requiring iterative estimations, as is the case with an early-late gate in a feedback loop. It is also desirable that the PN timing estimate is not required to be within a PN chip range, as is the case with the early-late gate method. It is further desirable for a PN timing implementation to allow asynchronous chip timing, which may be used for a continuous-time function that may contain discontinuities, and may not have a derivative at every point within its domain.